This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-089071, filed on Mar. 27, 2002 and the prior Japanese Patent Application No. 2002-327165, filed on Nov. 11, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and in particular, to a planar gate type Insulated Gate Bipolar Transistor (hereinafter referred to as IGBT).
2. Related Background Art
A market requirement for reducing loss in a semiconductor element for electric power has been stronger and an IGBT capable of controlling large electric power by a voltage driving is required to be further reduced in ON voltage.
FIG. 1 is a cross-sectional structural view of a conventional typical planar gate type IGBT.
The conventional typical planar gate type IGBT has a p+ type silicon substrate 11; a high-resistant nxe2x88x92 type layer 12 which is formed on the p+ type silicon substrate 11 and has a low impurity concentration; a plurality of p type base layers 13 which are formed at predetermined intervals in portions near the surface of the nxe2x88x92 type layer 12; n+ type emitter layers 14 each of which is formed in a portion near the surface in the vicinity of each of both ends of each p type base layer 13; channel regions 15 each of which is formed in each of both ends of each p type base layer 13; gate insulating films 16 each of which is formed on a region extending from one of the two channel regions 15 which are adjacent to each other via a portion near the surface of the nxe2x88x92 type layer 12 to the other; gate electrodes 17 each of which is formed on each of the gate insulating films 16; insulating films 21 each of which is formed on a region over the gate insulating film 16 so as to cover each gate electrode 17; emitter electrodes 18 each of which is formed so as to be in ohmic contact with the surfaces of the p type base layer 13 and the n+ type emitter layer 14 except for a portion covered with the gate insulating film 16; and a collector electrode 19 which is formed so as to be in ohmic contact with the reverse surface of the p+ type silicon substrate 11.
A method of manufacturing the conventional typical planar gate type IGBT shown in FIG. 1 is as follows.
First, the high-resistant nxe2x88x92 type layer 12 having a low impurity concentration is epitaxially grown on the p+ type silicon substrate 11.
After the nxe2x88x92 type layer 12 is formed, the plurality of base layers 13 are formed at predetermined intervals in portions near the surface of the nxe2x88x92 type layer 12 by diffusing impurities by a Diffusion Self Align (DSA) method. Further, the n+ type emitter layer 14 is formed in a portion near the surface in the vicinity of each of both ends of each p type base layer 13 by diffusing impurities by the same DSA method. That is, by using a diffusion opening used for forming the p type base layer 13 by diffusion, as it is, as a part of diffusion opening for forming the n+ type emitter layer 14 by diffusion, a double diffusion is performed to form the n+ type emitter layer 14 in a state where the channel regions 15 remain in a self-aligning manner in both end portions of each p type base layer 13.
After the p type base layers 13, the n+ type emitter layers 14 and the channel regions 15 are formed, each of the gate insulating films 16 is formed on the two channel regions 15 adjacent to each other via a portion near the surface of the nxe2x88x92 type layer 12, and the gate electrodes 17 are formed with polysilicon or aluminum on the gate insulating films 16. Further, the insulating films 21 for covering the respective gate electrodes 17 are formed on the regions over the gate insulating films 16.
After the gate insulating films 16, the gate electrodes 17 and the insulating films 21 are formed, the emitter electrodes 18 each of which is in ohmic contact with the surfaces of the p type base layer 13 and the n+ type emitter layer 14 except for a portion covered with the gate insulating film 16 are formed by evaporating or sputtering metal such as aluminum.
Further, the collector electrode 19 which is in ohmic contact with the reverse surface of the p+ type silicon substrate 11 is formed by evaporating or sputtering metal such as vanadium-nickel-gold (Vxe2x80x94Nixe2x80x94Au). In this manner, the conventional typical planar gate type IGBT shown in FIG. 1 is completed.
Various types of IGBTs have been developed and, for example, for the purpose of reducing a forward voltage, in order to increase a density of a small number of carriers on a negative electrode side, there is proposed an IGBT in which a shielding region is introduced around a base region (see, for example, Japanese Patent Publication No. 2000-509916).
The reducing ON voltage of the IGBT, as is the case with a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), has been achieved mainly by reducing a channel resistance by reducing the size of a unit cell by a micro pattern lithographic technique.
In the IGBT of a device having a small number of carriers, however, it has been known that the enlarging of the width of the gate electrode 17 can further reduce an emitter contact area per unit area to prevent holes implanted from the p+ type silicon substrate 11 to the nxe2x88x92 type layer 12 from being discharged more than necessary and to increase the carrier density of holes so as to compensate an electron accumulating layer produced under the gate electrode 17 according to an electric charge neutralizing condition, whereby resistance in this region is reduced to reduce the ON voltage as a result.
FIG. 2 is a cross-sectional structural view of a planar gate type IGBT in which the width of a gate electrode is enlarged. The structure and the manufacturing method of this planar gate type IGBT are the completely same as those of the planar gate type IGBT shown in FIG. 1, except for enlarging the width of the gate.
FIGS. 3A and 3B are graphs showing a carrier distribution along a line Y-Yxe2x80x2 in the cross-sectional structural view of the conventional planar gate type IGBT shown in FIG. 1 and FIG. 2.
As described above, by enlarging the width of the gate electrode 17 of the planar gate type IGBT, it is possible to reduce the ON voltage.
However, if the width of the gate electrode 17 is too much enlarged, a depletion layer produced in a blocking state at a pn junction of the p type base layer 13 and the nxe2x88x92 type layer 12 can not be pinched off between the p type base layer 13 and the p type base layer 13 which are adjacent to each other via the nxe2x88x92 type layer 12 to increase an electric field intensity. This phenomenon appears at a point in the graph shown in FIG. 3B where the carrier density on Y side is higher as compared with the graph in FIG. 3A. As a result, this reduces a withstand voltage, so it is impossible to make the width of the gate electrode 17 extremely wide. The enlarged width of the gate electrode 17 is limited to about 36 xcexcm for producing a withstand voltage of 600 V and 56 xcexcm for producing a withstand voltage of 1200 V.
Moreover, if the width of the gate electrode 17 is enlarged, an input capacity Cies and a feedback capacity Cres are increased. This might present also problems that a switching time is increased, or a collector current, a collector voltage and a gate voltage easily oscillate when a load is short-circuited and, in some case, leads to causing an oscillation breakdown.
A semiconductor device according to the first aspect of the present invention comprises:
a first conduction type first semiconductor layer;
a second conduction type second semiconductor layer which is formed on the first semiconductor layer and has a substantially uniform impurity concentration;
a plurality of first conduction type base layers formed in the surface of the second semiconductor layer;
a plurality of second conduction type emitter layers formed in the surface of the respective base layers;
channel regions formed in the surfaces of the respective base layers and between the emitter layers and the second semiconductor layer;
a first conduction type auxiliary base layer formed in the surface of the second semiconductor layer between the two base layers adjacent to each other;
a gate electrode formed via a gate insulating film on the second semiconductor layer between the auxiliary base layer and the two base layers and on the channel regions;
an emitter electrode connected to the base layers and the emitter layers; and
a collector electrode connected to the first semiconductor layer.
A semiconductor device according to the second aspect of the present invention comprises:
a first conduction type first semiconductor layer;
a second conduction type second semiconductor layer formed on the first semiconductor layer;
a plurality of first conduction type base layers formed in the surface of the second semiconductor layer;
a plurality of second conduction type emitter layers formed in the surface of the respective base layers;
channel regions formed in the surfaces of the respective base layers and between the emitter layers and the second semiconductor layer;
a first conduction type auxiliary base layer which is formed in the surface of the second semiconductor layer between the two base layers adjacent to each other and whose depth from the surface of the second semiconductor layer is nearly equal to a depth of the base layer;
a gate electrode formed via a gate insulating film on the second semiconductor layer between the auxiliary base layer and the two base layers and on the channel regions;
an emitter electrode connected to the base layers and the emitter layers; and
a collector electrode connected to the first semiconductor layer.
A semiconductor device according to the third aspect of the present invention comprises:
a first conduction type first semiconductor layer;
a second conduction type second semiconductor layer formed on the first semiconductor layer;
a plurality of first conduction type base layers formed in the surface of the second semiconductor layer;
a plurality of second conduction type emitter layers formed in the surface of the respective base layers;
channel regions formed in the surfaces of the respective base layers and between the emitter layers and the second semiconductor layer;
a plurality of first conduction type auxiliary base layers formed in the surface of the second semiconductor layer between the two base layers adjacent to each other;
a gate electrodes formed via a gate insulating film on the second semiconductor layer between the auxiliary base layers and the two base layers and on the channel regions;
an emitter electrode connected to the base layers and the emitter layers; and
a collector electrode connected to the first semiconductor layer.
A semiconductor device according to the fourth aspect of the present invention comprises:
a first conduction type first semiconductor layer;
a second conduction type second semiconductor layer formed on the first semiconductor layer;
a plurality of first conduction type base layers formed in the surface of the second semiconductor layer;
a plurality of second conduction type emitter layers formed in the surface of the respective base layers;
channel regions formed in the surfaces of the respective base layers and between the emitter layers and the second semiconductor layer;
a first conduction type auxiliary base layer formed in the surface of the second semiconductor layer between the two base layers adjacent to each other;
a gate electrode formed on a region extending from one of the two channel regions between the auxiliary base layer and the two base layers to the other;
an emitter electrode connected to the base layers and the emitter layers; and
a collector electrode connected to the first semiconductor layer.